Memory devices such as, for example, semiconductor random access memory (RAM) circuits store logic states by applying either high or low voltage levels to memory cell transistors that form a memory cell array. A static random access memory (“SRAM”) array is basically constructed of memory cells as storage units arranged at the intersections of a plurality of word lines arranged in the row direction and a plurality of bit lines arranged in the column direction. In a “read” operation, a read voltage is applied to the gate of the memory cell, and the corresponding indication of whether the memory cell turns on (e.g., conducts current) indicates the programming state of the memory cell, e.g. a memory cell that conducts current during the “read” operation may be assigned a digital value of “1,” and a memory cell that does not conduct current during the “read” operation may be assigned a digital value of “0”.
In order to control the application of voltage to the gate lines of selected cells in a memory cell array, gate line, i.e. word line voltage control circuits are typically employed. In general, memory cells are accessible by applying activation voltages to word lines and bit lines (drain lines). In this regard, word lines are typically used to activate memory cells and bit lines to provide data to or retrieve data from activated memory cells. In a word line voltage control circuit, high and low (or negative) voltage levels may be applied to selected word lines of a memory cell array by a decoder circuit (e.g., a word line driver) in order to activate selected memory cells. In other words, when memory access is desired, an activation voltage may be applied to the corresponding word line by the word line driver to perform the desired function (e.g., read or write). In some cases, when memory access is not needed, the word line driver may apply a deactivation voltage to cease memory access function. The word line driver circuit/cell is therefore one of the most crucial circuits in a memory array.
Various word line driver cell designs have been used. Current designs often require relatively large area footprints due to the inclusion of a large number of transistors, however. Conventional word line drivers therefore often take up a relatively large area.
Word line driver cells may include multiple levels of metal interconnect layers. Transistors formed in the word line driver cells typically have polysilicon gates and may be longitudinally spaced. The word lines are generally metallic and connect the gates of transistors of a certain row in the array. Because of various design rules and limitations in the photographic processes available, one shortcoming of current methods and design layouts is that multiple layers of metallization must be utilized for the word lines because of various design rules and limitations in the photographic processes available. This limits the availability of multiple metal layers from being used for other purposes. Another shortcoming is that word line driver cells take up a large area at the expense of other device features at a time when there is a push to increase levels of integration and fit more components into a smaller area.